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5AGXMD3G631I4N 参数 Datasheet PDF下载

5AGXMD3G631I4N图片预览
型号: 5AGXMD3G631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Overview for the Arria V Device Family  
1–15  
Clock Networks and PLL Clock Sources  
Clock Networks and PLL Clock Sources  
The Arria V clock network architecture is based on Altera’s proven global, quadrant,  
and peripheral clock structure, which is supported by dedicated clock input pins and  
fractional PLLs. Arria V devices have 16 global clock networks capable of up to  
625 MHz operation. The Quartus II software identifies all unused sections of the clock  
network and powers them down, which reduces power consumption.  
Arria V devices have up to 16 PLLs with 18 output counters per PLL. One fractional  
PLL can use up to 18 output counters and two adjacent fractional PLLs share the 18  
output counters. You can use fractional PLLs to reduce the number of oscillators  
required on your board, as well as reduce the clock pins used in the device by  
synthesizing multiple clock frequencies from a single reference clock source. You can  
use the PLLs for frequency synthesis, on-chip clock deskew, jitter attenuation,  
dynamic phase-shift, zero delay buffers, counters reconfiguration, bandwidth  
reconfiguration, programmable output clock duty cycles, PLL cascading, and  
reference clock switchover.  
Arria V devices use a fractional PLL architecture in addition to the historical integer  
PLL. When you use fractional PLL mode, you can use the PLLs for precision  
fractional-N frequency synthesis—removing the need for an off-chip reference clock.  
Transceiver fractional PLLs, when not used by the Transceiver I/O, can be used as  
general-purpose fractional PLLs by the FPGA fabric.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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