AV-51001
2013.05.06
Package Plan
9
Package Plan
Table 7: Package Plan for Arria V GT Devices—Preliminary
F672
Mem-
ber
Code
(27 mm)
XCVR
GPIO
6-Gbps
10-
Gbps
GPIO
F896
(31 mm)
XCVR
6-Gbps
10-
Gbps
GPIO
F1152
(35 mm)
XCVR
6-Gbps
10-
Gbps
GPIO
F1517
(40 mm)
XCVR
6-Gbps
10-
Gbps
C3
C7
D3
D7
336
—
—
—
3 (9)
—
—
—
4
—
—
—
416
384
384
—
3 (9)
6 (18)
6 (18)
—
4
8
8
—
—
544
544
544
—
6 (24)
6 (24)
6 (24)
—
12
12
12
—
—
704
704
—
—
6 (24)
6 (36)
—
—
12
20
The 6-Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10-Gbps
channels as three 6-Gbps channels—the total number of 6-Gbps channels are shown in brackets. For example,
you can also configure the Arria V GT D7 device in the F1517 package with nine 6-Gbps and eighteen
10-Gbps, twelve 6-Gbps and sixteen 10-Gbps, fifteen 6-Gbps and fourteen 10-Gbps, or up to thirty-six
6-Gbps with no 10-Gbps channels.
Arria V GZ
This section provides the available options, maximum resource counts, and package plan for the Arria V GZ
devices.
Available Options
Figure 3: Sample Ordering Code and Available Options for Arria V GZ Devices—Preliminary
Transceiver Count
Maximum channels
Embedded Hard IPs
M : 1 hard PCIe controller
E : 12
H : 24
K : 36
Package Type
F : FineLine BGA (FBGA)
H : Hybrid FBGA
Operating Temperature
C : Commercial (T
J
= 0° C to 85° C)
I : Industrial (T
J
= -40° C to 100° C)
Family Signature
5A : Arria V
5A
GZ
M
E7
K
2
F
40
C
3
N
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
L : Low-power device
FPGA Fabric
Speed Grade
3 (fastest)
4
Family Variant
GZ : 12.5-Gbps transceivers
Member Code
E1 : 220K logic elements
E3 : 360K logic elements
E5 : 400K logic elements
E7 : 450K logic elements
Transceiver
Speed Grade
2 : 12.5 Gbps
3 : 10.3125 Gbps
Package Code
29 : 780 pins
35 : 1,152 pins
40 : 1,517 pins
Note:
Low-power device option is available only for –3 speed grade at industrial temperature
Arria V Device Overview
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