AV-51001
2013.05.06
36
Document Revision History
Date
Version
Changes
November 2012
2012.11.19 • Updated the summary of features.
• Updated Arria V GZ information regarding 3.3 V I/O support.
• Removed Arria V GZ engineering sample ordering code.
• Updated the maximum resource counts for Arria V GX and GZ.
• Updated Arria V ST ordering codes for transceiver count.
• Updated transceiver counts for Arria V ST packages.
• Added simplified floorplan diagrams for Arria V GZ, SX, and ST.
• Added FPP x32 configuration mode for Arria V GZ only.
• Updated CvP (PCIe) remote system update support information.
• Added HPS external memory performance information.
• Updated template.
October 2012
3.0
• Added Arria V GZ information.
• Updated Table 1, Table 2, Table 3, Table 14, Table 15, Table 16, Table
17, Table 18, Table 19, Table 20, and Table 21.
• Added the “Arria V GZ” section.
• Added Table 8, Table 9 and Table 22.
July 2012
June 2012
2.1
2.0
• Added –I3 speed grade to Figure 1 for Arria V GX devices.
• Updated the 6-Gbps transceiver speed from 6.553 Gbps to 6.5536 Gbps
in Figure 3 and Figure 1.
• Restructured the document.
• Added the “Embedded Memory Capacity” and “Embedded Memory
Configurations” sections.
• Added Table 1, Table 3, Table 12, Table 15, and Table 16.
• Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9,
Table 10, Table 11, Table 13, Table 14, and Table 19.
• Updated Figure 1, Figure 2, Figure 3, Figure 4, and Figure 8.
• Updated the “FPGA Configuration and Processor Booting” and
“Hardware and Software Development” sections.
• Text edits throughout the document.
February 2012
December 2011
1.3
1.2
• Updated Table 1–7 and Table 1–8.
• Updated Figure 1–9 and Figure 1–10.
• Minor text edits.
Minor text edits.
Arria V Device Overview
Altera Corporation
Feedback
ALTERA [ ALTERA CORPORATION ]
