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5AGXMA1D431C3ES 参数 Datasheet PDF下载

5AGXMA1D431C3ES图片预览
型号: 5AGXMA1D431C3ES
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件概述 [Arria V Device Overview]
分类和应用:
文件页数/大小: 37 页 / 793 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2013.05.06  
10  
Maximum Resources  
Maximum Resources  
Table 8: Maximum Resource Counts for Arria V GZ DevicesPreliminary  
Member Code  
Resource  
E1  
220  
E3  
360  
E5  
400  
E7  
Logic Elements (LE) (K)  
450  
ALM  
83,020  
332,080  
11,700  
2,594  
800  
135,840  
543,360  
19,140  
4,245  
1,044  
2,088  
20  
150,960  
603,840  
28,800  
4,718  
1,092  
2,184  
24  
169,800  
679,200  
34,000  
5,306  
1,139  
2,278  
24  
Register  
M20K  
MLAB  
Memory (Kb)  
Variable-precision DSP Block  
18 x 18 Multiplier  
PLL9  
1,600  
20  
12.5 Gbps Transceiver  
GPIO10  
24  
24  
36  
36  
414  
414  
674  
674  
Transmitter  
Receiver  
99  
99  
166  
166  
LVDS11  
108  
108  
168  
168  
PCIe Hard IP Block  
1
1
1
1
Related Information  
High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook  
Provides the number of LVDS channels in each device package.  
Package Plan  
Table 9: Package Plan for Arria V GZ DevicesPreliminary  
H780  
F1152  
(35 mm)  
F1517  
(29 mm)  
(40 mm)  
Member Code  
GPIO  
342  
342  
XCVR  
12  
GPIO  
414  
414  
534  
534  
XCVR  
24  
GPIO  
XCVR  
E1  
E3  
E5  
E7  
12  
24  
24  
674  
674  
36  
24  
36  
9
The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs.  
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os  
includes transceiver I/Os.  
10  
11  
Arria V Device Overview  
Altera Corporation  
Feedback  
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