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5AGXFD3D427C4N 参数 Datasheet PDF下载

5AGXFD3D427C4N图片预览
型号: 5AGXFD3D427C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Arria V Devices  
2–17  
Switching Characteristics  
(1)  
Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary  
(Part 3 of 3)  
–5  
–4  
–6  
Commercial  
Speed Grade  
Commercial/Industrial  
Speed Grade  
Commercial Speed  
Grade  
Symbol/  
Description  
Conditions  
Unit  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Transmitter  
Supported I/O  
Standards  
1.5 V PCML  
Data rate  
VOCM  
611  
6553  
611  
6553  
611  
3125  
Mbps  
mV  
30  
30  
650  
85  
30  
30  
650  
85  
30  
30  
650  
85  
85-setting  
100-setting  
120-setting  
150-setting  
100  
120  
150  
100  
120  
150  
100  
120  
150  
Differential on-chip  
termination resistors  
(7)  
Rise time  
160  
160  
160  
160  
160  
160  
ps  
(7)  
Fall time  
ps  
CMU PLL  
Supported data range  
611  
6553  
611  
6553  
611  
3125  
Mbps  
Transceiver-FPGA Fabric Interface  
Interface speed  
25  
25  
187.50  
163.84  
25  
25  
163.84  
163.84  
25  
25  
156.25  
156.25  
MHz  
MHz  
(single-width mode)  
Interface speed  
(double-width mode)  
Notes to Table 2–20:  
(1) Speed grades shown in Table 2–20 refer to the Transceiver Speed Grade in the device ordering code. For more information about device ordering codes, refer  
to the Overview for Arria V Device Family chapter.  
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.  
(3) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.  
(4) The device cannot tolerate prolonged operation at this absolute maximum.  
(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the  
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.  
(6) The rate match FIFO supports only up to 300 parts per million (ppm).  
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet