2–30
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Memory Block Specifications
Table 2–27 lists the Arria V memory block specifications.
Table 2–27. Memory Block Performance Specifications for Arria V Devices—Preliminary (1), (2)
Resources Used
Performance
C5,I5
Memory
Mode
Unit
C4
C6
ALUTs
Memory
Speed Grade Speed Grade Speed Grade
Single port, all supported widths
0
0
1
1
500
450
400
MHz
MHz
Simple dual-port, all supported
widths
500
450
400
MLAB
Simple dual-port with read and
write at the same address
0
1
400
350
300
MHz
ROM, all supported width
—
0
—
1
500
400
450
350
400
285
MHz
MHz
Single-port, all supported widths
Simple dual-port, all supported
widths
0
0
0
1
1
1
400
315
400
350
275
350
285
240
285
MHz
MHz
MHz
Simple dual-port with the
read-during-write option set to
Old Data, all supported widths
M10K
Block
True dual port, all supported
widths
ROM, all supported widths
0
1
400
1,275
850
350
285
MHz
ps
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
—
—
—
—
1,360
1,060
1,445
1,175
ps
Notes to Table 2–27:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX
.
Temperature Sensing Diode Specifications
Table 2–28 lists the specifications for the Arria V internal temperature sensing diode.
Table 2–28. Internal Temperature Sensing Diode Specifications for Arria V Devices—Preliminary
Offset
Temperature
Range
Conversion
Time
Minimum Resolution with no
Missing Codes
Accuracy Calibrated Sampling Rate
Option
Resolution
Frequency:
1 MHz
–40 to 100°C
8°C
No
< 100 ms
8 bits
8 bits
Arria V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
