5AGXFA3D427C4N 参数 Datasheet PDF下载

AV-51001

2013.05.06

Package Plan

7

Package Plan

Table 5: Package Plan for Arria V GX Devices—Preliminary

F672

Member

Code

(27 mm)

GPIO

XCVR

F896

4

F1152

(35 mm)

GPIO

XCVR

F1517

(40 mm)

GPIO

XCVR

(31 mm)

GPIO

XCVR

A1

A3

A5

A7

B1

B3

B5

B7

336

336

336

336

—

—

—

—

9

9

9

9

—

—

—

—

416

416

384

384

384

384

—

—

9

9

18

18

18

18

—

—

—

—

544

544

544

544

544

544

—

—

24

24

24

24

24

24

—

—

—

—

704

704

704

704

—

—

—

—

24

24

36

36

Arria V GT

This section provides the available options, maximum resource counts, and package plan for the Arria V GT

devices.

Available Options

Figure 2: Sample Ordering Code and Available Options for Arria V GT Devices—Preliminary

Embedded Hard IPs

M : 1 hard PCIe and 2 hard

memory controllers

F : Maximum 2 hard PCIe and

4 hard memory controllers

Transceiver Count

Maximum channels

D

G

H

K

:

:

:

:

9

18

24

36

Package Type

F : FineLine BGA (FBGA)

Operating Temperature

I

: Industrial (T

J

= -40° C to 100° C)

Family Signature

5A : Arria V

5A

GT

F

D7

K

3

F

40

I

3

N

Optional Suffix

Indicates specific device

options or shipment method

N : Lead-free packaging

ES : Engineering sample

FPGA Fabric

Speed Grade

3 (fastest)

5

Family Variant

GT : 10-Gbps transceivers

Member Code

C3 : 156K logic elements

C7 : 242K logic elements

D3 : 362K logic elements

D7 : 504K logic elements

Transceiver

Speed Grade

3 : 10.3125 Gbps

Package Code

27 : 672 pins

31 : 896 pins

35 : 1,152 pins

40 : 1,517 pins

4

In the F896 package, the PCIe hard IP block on the right side of the Arria V GX A5, A7, B1, and B3 devices

support x1 for Gen1 and Gen2 data rates.

Altera Corporation

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