8
Maximum Resources
AV-51001
2013.05.06
Maximum Resources
Table 6: Maximum Resource Counts for Arria V GT Devices—Preliminary
Resource
Member Code
C3
C7
D3
D7
Logic Elements (LE) (K)
ALM
Register
Memory (Kb)
M10K
MLAB
156
58,900
235,600
10,510
961
396
792
10
242
91,680
366,720
13,660
1,448
800
1,600
12
6 (24)
12
544
120
136
2
4
362
136,880
547,520
17,260
2,098
1,045
2,090
12
6 (24)
12
704
160
176
2
4
504
190,240
760,960
24,140
2,906
1,156
2,312
16
6 (36)
20
704
160
176
2
4
Variable-precision DSP Block
18 x 18 Multiplier
PLL
5
Transceiver
GPIO
8
LVDS
PCIe Hard IP Block
Hard Memory Controller
Related Information
6 Gbps
6
10 Gbps
7
3 (9)
4
416
Transmitter
Receiver
68
80
1
2
Provides the number of LVDS channels in each device package.
Describes 10 Gbps channels usage conditions.
5
6
7
8
The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs.
The 6 Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10 Gbps
channels as three 6 Gbps channels-the total number of 6 Gbps channels are shown in brackets.
Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture
in Arria V Devices chapter. For information about 10 Gbps SFF-8431 compliance, contact Altera.
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os
includes transceiver I/Os.
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