Chapter 2: Device Datasheet for Arria V Devices
2–47
I/O Timing
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
f
You can download the Excel-based I/O Timing spreadsheet from the Arria V Devices
Literature webpage.
Programmable IOE Delay
Table 2–46 lists the Arria V IOE programmable delay settings.
Table 2–46. IOE Programmable Delay for Arria V Devices (1)
Fast Model
Slow Model
Available
Settings
Minimum
Offset
Parameter
Unit
Industrial
Commercial
TBD
C4
C5, I5
TBD
TBD
TBD
TBD
TBD
C6
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Note to Table 2–46:
(1) Pending the Quartus II software extraction.
Programmable Output Buffer Delay
Table 2–47 lists the delay chain settings that control the rising and falling edge delays
of the output buffer. The default delay is 0 ps.
(1), (2)
Table 2–47. Programmable Output Buffer Delay—Preliminary
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
Rising and/or falling edge
delay
DOUTBUF
100
ps
150
ps
Notes to Table 2–47:
(1) Pending the Quartus II software extraction.
(2) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
February 2012 Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
