2–36
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
(1)
Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary
(Part 2 of 2)
–6
–4
–5
Clock
Network
Speed Grade
Speed Grade
Speed Grade
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Duty cycle jitter
Global
tJIT(duty)
–75
75
–90
90
–90
90
ps
Note to Table 2–33:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
OCT Calibration Block Specifications
Table 2–34 lists the OCT calibration block specifications for Arria V devices.
Table 2–34. OCT Calibration Block Specifications for Arria V Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTCAL
—
—
1000
32
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
TOCTSHIFT
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
TRS_RT
—
2.5
—
ns
Figure 2–4 shows the TRS_RT for dyn_term_ctrland oesignals.
Figure 2–4. Timing Diagram for dyn_term_ctrl and oe Signals
Tristate
Tristate
RX
oe
RX
dyn_term_ctrl
TRS_RT
TRS_RT
Duty Cycle Distortion (DCD) Specifications
Table 2–35 lists the worst-case DCD for Arria V devices.
Table 2–35. Worst-Case DCD on Arria V I/O Pins—Preliminary
–C5,I5 Speed
–C6 Speed
Grade
–C4 Speed Grade
Grade
Symbol
Unit
Min
Max
Min
Max
Min
45
Max
Output Duty Cycle
45
55
45
55
55
%
Arria V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
