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5AGTMB1D631I4N 参数 Datasheet PDF下载

5AGTMB1D631I4N图片预览
型号: 5AGTMB1D631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Overview for the Arria V Device Family  
1–21  
Document Revision History  
Figure 1–6. Ordering Information for Arria V SX and ST Devices  
Transceiver Count  
SX Variant  
(6-Gbps)  
Embedded Hard IPs  
D
E
: 9  
: 12  
PackageType  
B
: No hard PCIe or hard  
memory controller  
F
: FineLine BGA (FBGA)  
G : 18  
: 24  
ST Variant  
M : 1 hard PCIe and 2 hard  
memory controller  
H
OperatingTemperature  
F
: Maximum 2 hard PCIe and  
3 hard memory controllers  
(6-Gbps, 10-Gbps)  
C
I
: Commercial temperature (TJ = 0° C to 85° C)  
: Industrial temperature (TJ = -40° C to 100° C)  
E
: 6, 2  
G : 18, 2  
: 12, 6  
(These numbers do not include the  
hard memory controllers in the HPS)  
K
Optional Suffix  
Indicates specific device  
options or shipment method  
Family Signature  
5A : Arria V  
5A  
ST  
F
D5  
K
4
F
40  
I
5
N
N
: Lead-free packaging  
ES : Engineering sample  
FPGA Fabric Speed Grade  
Family Variant  
SX : 6-Gbps transceivers  
ST : 10-Gbps transceivers  
Package Code  
SX Variant  
4 (fastest)  
FBGA PackageType  
31 : 896 pins  
Member Code  
5
6
35 : 1,152 pins  
40 : 1,517 pins  
SX Variant  
B3 : 350K logic elements  
B5 : 460K logic elements  
Transceiver Speed Grade  
SX Variant  
ST Variant  
5
4
6
: 6-Gbps  
: 3-Gbps  
ST Variant  
D3 : 350K logic elements  
D5 : 460K logic elements  
ST Variant  
: 10-Gbps  
3
Document Revision History  
Table 1–12 lists the revision history for this chapter.  
Table 1–12. Document Revision History  
Date  
Version  
1.3  
Changes  
Updated Table 1–2 and Table 1–3.  
Updated Figure 1–5 and Figure 1–6.  
Minor text edits.  
February 2012  
December 2011  
1.2  
Minor text edits.  
Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–6, Table 1–7, Table 1–9, and  
Table 1–10.  
Added “SoC FPGA with HPS” section.  
Updated “Clock Networks and PLL Clock Sources” and “Ordering Information” sections.  
November 2011  
August 2011  
1.1  
1.0  
Updated Figure 1–5.  
Added Figure 1–6.  
Minor text edits.  
Initial release.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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