1–10
Chapter 1: Overview for the Arria V Device Family
PCIe Gen1 and Gen2 Hard IP
PCIe Gen1 and Gen2 Hard IP
Arria V devices contain PCIe hard IP designed for performance, ease-of-use, and
increased functionality. The PCIe hard IP consists of the PHY MAC, data link, and
transaction layers. The PCIe hard IP supports PCIe Gen2 end point and root port for
up to x4 lane configurations, and PCIe Gen1 end point and root port for up to x8 lane
configurations. PCIe endpoint support includes multifunction support for up to eight
functions, as shown in Figure 1–2.
Figure 1–2. PCIe Multifunction for Arria V Devices
FPGA
Host CPU
PCIe Link
Root
Complex
Local
Local
Periph 1
Periph 2
The Arria V PCIe hard IP operates independently from the core logic, which allows
the PCIe link to wake up and complete link training in less than 100 ms, while the
Arria V device completes loading the programming file for the rest of the device. In
addition, the Arria V PCIe hard IP has improved end-to-end data path protection
using ECC.
FPGA GPIOs
Arria V devices offer highly configurable GPIOs. The following list describes the
many features of the GPIOs:
■
Programmable bus hold and weak pull-up.
■
LVDS output buffer with programmable differential output voltage (VOD) and
programmable pre-emphasis.
■
■
Dynamic on-chip parallel termination (RT OCT) for all I/O banks with OCT
calibration to limit the termination impedance variation.
On-chip dynamic termination to swap between serial and parallel termination,
depending on whether there is reading or writing on a common bus for signal
integrity.
■
■
Configurable unused voltage reference (VREF) pins as user I/Os.
Easy timing closure support using the hardened read FIFO in the input register
path, and delay-locked loop (DLL) delay chain with fine and coarse architecture.
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
