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5AGTMB1D431C4N 参数 Datasheet PDF下载

5AGTMB1D431C4N图片预览
型号: 5AGTMB1D431C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Arria V Devices  
2–41  
Configuration Specification  
FPP Configuration Timing when DCLK to DATA[] > 1  
Figure 2–6 shows the timing waveform for a FPP configuration when using a MAX II  
device or microprocessor as an external host. This waveform shows timing when the  
DCLK-to-DATA[]ratio is more than 1.  
(1), (2)  
Figure 2–6. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1  
tCF2ST1  
tCFG  
tCF2CK  
nCONFIG  
nSTATUS (3)  
tSTATUS  
tCF2ST0  
CONF_DONE (4)  
t
CL  
tCF2CD  
(8)  
tST2CK  
t
CH  
DCLK (6)  
DATA[15..0] (8)  
User I/O  
(7)  
(5)  
1
2
1
1
2
r
1
2
r
r
t
CLK  
n
Word 0  
Word 1  
Word (n-1) Word  
User Mode  
User Mode  
Word 3  
t
t
tDSU  
DH  
DH  
High-Z  
(9)  
INIT_DONE  
tCD2UM  
Notes to Figure 2–6:  
(1) To find the DCLK-to-DATA[]ratio for your system, refer Table 2–38 on page 2–38.  
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONEare at logic high levels.  
When nCONFIGis pulled low, a reconfiguration cycle begins.  
(3) After power up, the Arria V device holds nSTATUSlow for the time as specified by the POR delay.  
(4) After power up, before and during configuration, CONF_DONEis low.  
(5) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.  
(6) “r” denotes the DCLK-to-DATA[]ratio. For the DCLK-to-DATA[]ratio based on the decompression and the design security feature enable  
settings, refer to Table 2–38 on page 2–38.  
(7) If needed, pause DCLKby holding it low. When DCLKrestarts, the external host must provide data on the DATA[15..0]pins prior to sending  
the first DCLKrising edge.  
(8) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high after the Arria V device  
receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization  
and enter user mode.  
(9) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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