1. Overview for the Arria V Device Family
February 2012
AV51001-1.3
AV51001-1.3
Built on the 28-nm low-power process technology, Arria® V devices offer the lowest
power and lowest system cost for mainstream applications. Arria V devices include
unique innovations such as the lowest static power in its class, the lowest power
transceivers of any midrange family, support for serial data rates up to
10.3125 gigabits per second (Gbps), a powerful collection of integrated hard
intellectual property (IP), and a power-optimized core architecture, making Arria V
devices ideal for the following applications:
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Power sensitive wireless infrastructure equipment
20G/40G bridging, switching, and packet processing applications
High-definition video processing and image manipulation
Intensive digital signal processing (DSP) applications
Arria V devices are available in the following variants:
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Arria V GX—FPGA with integrated 6-Gbps transceivers, this variant provides
bandwidth, cost, and power levels that are optimized for high-volume data and
signal-processing applications.
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Arria V GT—FPGA with integrated 10-Gbps transceivers, this variant provides
enhanced high-speed serial I/O bandwidth for cost-sensitive data and signal
processing applications.
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Arria V SX—system-on-a-chip (SoC) FPGA with integrated Arria V FPGA and
ARM®-based hard processor system (HPS).
Arria V ST—SoC FPGA with integrated Arria V FPGA, ARM-based HPS, and
10-Gbps transceivers.
The Arria V SoC FPGA variants feature an FPGA integrated with an HPS that consists
of a dual-core ARM Cortex™-A9 MPCore™ processor, a rich set of peripherals, and a
shared multiport SDRAM memory controller.
The unique feature set in Arria V devices was chosen to optimize power, cost, and
performance. These features include a redesigned adaptive logic module (ALM),
distributed memory, new 10-Kbit (M10K) internal memory blocks, variable-precision
DSP blocks, and fractional clock synthesis phase-locked loops (PLLs) with a highly
flexible clocking network, all interconnected by a power-optimized MultiTrack
routing architecture.
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Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012
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