Chapter 1: Overview for the Arria V Device Family
1–17
SoC FPGA with HPS
Arria V transceivers are also designed for power efficiency. As a result, the transceiver
channels consume 50% less power than the previous generation of Arria devices.
SoC FPGA with HPS
Each SoC FPGA device combines an FPGA fabric and an HPS in a single device. This
combination delivers the flexibility of programmable logic with the power and cost
savings of hard IP in the following ways:
■
■
■
Reduces board space, system power, and bill of materials cost by eliminating a
discrete embedded processor
Allows you to differentiate the end product in both the hardware and software,
and to support virtually any interface standard
Extends the product life and revenue through in-field hardware and software
updates
Features of the HPS
The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of
peripherals, and a shared multiport SDRAM memory controller, as shown in
Figure 1–4..
Figure 1–4. HPS with Dual-Core ARM Cortex-A9 MPCore Processor
Configuration
Controller
Lightweight
HPS-to-FPGA
FPGA Fabric
FPGA-to-HPS HPS-to-FPGA
FPGA-to-HPS SDRAM
FPGA
Manager
HPS
Ethernet
MAC (2x)
ARM Cortex-A9 MPCore
CPU0
(ARM Cortex-A9
with NEON/FPU,
CPU1
(ARM Cortex-A9
with NEON/FPU,
USB
OTG (2x)
64 KB
Boot
ROM
32 KB Instruction Cache, 32 KB Instruction Cache,
32 KB Data Cache, and 32 KB Data Cache, and
Memory Management Unit) Memory Management Unit)
NAND Flash
Controller
Multiport
DDR SDRAM
Controller
with
SD/MMC/SDIO
Controller
Level 3
Interconnect
ACP
SCU
Optional ECC
DMA
Controller
L2 Cache (512 KB)
64 KB
On-Chip
RAM
ETR
(Trace)
Debug
Access Port
Low Speed Peripherals
(Timers, GPIOs, UART, SPI, I2C, Quad SPI Flash Controller, System Manager, Clock Manager, Reset Manager, and Scan Manager)
February 2012 Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
