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5AGTFB1D627C4N 参数 Datasheet PDF下载

5AGTFB1D627C4N图片预览
型号: 5AGTFB1D627C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Arria V Devices  
2–43  
Configuration Specification  
AS Configuration Timing  
Figure 2–7 shows the timing waveform for the active serial (AS) x1 mode and AS x4  
mode configuration timing.  
Figure 2–7. AS Configuration Timing  
t
(1)  
POR  
nCONFIG  
nSTATUS  
CONF_DONE  
nCSO  
DCLK  
t
CO  
t
DH  
Read Address  
AS_DATA0/ASDO  
AS_DATA1 (2)  
t
SU  
bit 1  
bit 0  
bit N - 1  
bit N  
t
(3)  
CD2UM  
INIT_DONE (4)  
User I/O  
User Mode  
Notes to Figure 2–7:  
(1) The AS scheme supports standard and fast POR delay (tPOR). For tPOR delay information, refer to the “POR Delay Specification” section in the  
Configuration, Design Security, and remote System Upgrades in Arria V Devices chapter.  
(2) If you are using AS x4 mode, this signal represents the AS_DATA[3..0]and EPCQ sends in 4-bits of data for each DCLKcycle.  
(3) The initialization clock can be from the internal oscillator or CLKUSRpin.  
(4) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.  
Table 2–41 lists the timing parameters for AS x1 and AS x4 configurations in Arria V  
devices.  
(1), (2)  
Table 2–41. AS Timing Parameters for AS x1 and x4 Configurations in Arria V Devices—Preliminary  
Symbol  
tCO  
Parameter  
Minimum  
Maximum  
Unit  
µs  
DCLK falling edge to the AS_DATA0  
/
ASDOoutput  
4
tSU  
Data setup time before the rising edge on DCLK  
Data hold time after the rising edge on DCLK  
CONF_DONEhigh to user mode  
1.5  
ns  
tH  
0
175  
ns  
tCD2UM  
tCD2CU  
tCD2UMC  
437  
µs  
CONF_DONEhigh to CLKUSRenabled  
4 x maximum DCLKperiod  
t
CD2CU + (Tinit x CLKUSR  
CONF_DONEhigh to user mode with CLKUSR  
option on  
period)  
Number of clock cycles required for device  
initialization  
Tinit  
17,408  
Cycles  
Notes to Table 2–41:  
(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.  
(2) The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in Table 2–43 on  
page 2–45.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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