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5AGTFB1D627C4N 参数 Datasheet PDF下载

5AGTFB1D627C4N图片预览
型号: 5AGTFB1D627C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–38  
Chapter 2: Device Datasheet for Arria V Devices  
Configuration Specification  
FPP Configuration Timing  
This section describes the fast passive parallel (FPP) configuration timing parameters  
for Arria V devices.  
DCLK-to-DATA[] Ratio (r) for FPP Configuration  
FPP configuration requires a different DCLK-to-DATA[]ratio when you turn on  
encryption or the compression feature.  
Table 2–38 lists the DCLK-to-DATA[]ratio for each combination.  
Table 2–38. DCLK-to-DATA[] Ratio for Arria V Devices (1)  
Configuration Scheme  
Encryption  
Compression  
DCLK-to-DATA[] ratio (r)  
Off  
On  
Off  
On  
Off  
On  
Off  
On  
Off  
Off  
On  
On  
Off  
Off  
On  
On  
1
1
2
2
1
2
4
4
FPP (8-bit wide)  
FPP (16-bit wide)  
Note to Table 2–38:  
(1) Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the DATA[]rate in  
byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLKfrequency  
must be 2 times the DATA[]rate in Wps.  
FPP Configuration Timing when DCLK to DATA[] = 1  
Figure 2–5 shows the timing waveform for a FPP configuration when using a MAX® II  
device as an external host. This timing waveform shows timing when the DCLK-to-  
DATA[]ratio is 1.  
1
When you enable decompression or the design security feature, the DCLK-to-DATA[]  
ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[]ratio, refer to  
Table 2–38.  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
February 2012 Altera Corporation  
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