Chapter 2: Device Datasheet for Arria V Devices
2–15
Switching Characteristics
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 2–20 and Table 2–21 list the Arria V transceiver specifications.
(1)
Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary
(Part 1 of 3)
–4
–5
–6
Commercial
Speed Grade
Commercial/Industrial
Speed Grade
Commercial Speed
Grade
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2), HCSL, and LVDS
Input frequency from
REFCLKinput pins
—
—
—
27
45
—
—
—
710
55
27
45
—
—
—
710
55
27
45
—
—
—
710
55
MHz
%
Duty cycle
Peak-to-peak
differential input voltage
200
2000
200
2000
200
2000
mV
Spread-spectrum
modulating clock
frequency
PCI Express®
(PCIe®)
30
—
33
30
—
33
30
—
33
kHz
—
0 to
0 to
0 to
Spread-spectrum
downspread
PCIe
—
—
—
—
—
—
—
—
—
—
—
—
–0.5%
–0.5%
–0.5%
On-chip termination
resistors
—
—
100
100
100
(3)
(3)
VICM (AC coupled)
1.1
1.1 (3)
1.1
V
HCSL I/O
standard for the
PCIe reference
clock
VICM (DC coupled)
250
—
—
550
—
250
—
—
550
—
250
—
—
550
—
mV
2000
1%
2000
1%
2000
1%
RREF
—
Transceiver Clocks
fixedclkclock
frequency
Avalon®-Memory-
Mapped (Avalon-MM)
PHY management clock
frequency
PCIe
Receiver Detect
—
125
—
—
125
—
—
125
—
MHz
MHz
< 150
February 2012 Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
