1–8
Chapter 1: Overview for the Arria V Device Family
Low-Power Serial Transceivers
PMA Support
To prevent core and I/O noise from coupling into the transceivers, the PMA block is
isolated from the rest of the chip, ensuring optimal signal integrity. The transceiver
channels consist of the PMA, PCS, and clock networks. You can also use the unused
receiver PMA channels as additional transmit PLLs.
Table 1–5 lists the transceiver PMA features.
Table 1–5. Transceiver PMA Features for Arria V Devices
Features
Capability
Up to 16” FR4 PCB fabric drive capability at up
to 6.5536 Gbps
Backplane support
Chip-to-chip support
Up to 10.3125 Gbps
PLL-based clock recovery
Superior jitter tolerance
Programmable serializer and deserializer
(SERDES)
Flexible SERDES width
Up to 6 dB of pre-emphasis and 4 dB of
equalization
Equalization and pre-emphasis
Ring oscillator transmit PLLs
Input reference clock range
611 Mbps to 10.3125 Gbps
27 MHz to 710 MHz
Allows reconfiguration of single channels
without affecting operation of other channels
Transceiver dynamic reconfiguration
PCS Support
The Arria V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, or 40-bit
interface, depending on the transceiver data rate and protocol. Arria V devices
contain PCS hard IP to support PCIe Gen1 and Gen2, XAUI, GbE, Serial
RapidIO® (SRIO), and CPRI protocols. All other standard and proprietary protocols
from 611 Mbps to 6.5536 Gbps are supported through the custom double-width mode
(up to 6.5536 Gbps) and custom single-width mode (up to 3.75 Gbps) transceiver PCS
hard IP. A dedicated 80-bit interface to the core logic connects directly from the PMA,
bypassing the PCS hard IP, to support all protocols beyond 6.5536 Gbps up to 10.3125
Gbps.
Table 1–6 lists the transceiver PCS features.
Table 1–6. Transceiver PCS Features for Arria V Devices (Part 1 of 2)
(1)
PCS Support
Data Rates (Gbps)
Transmitter Data Path
Receiver Data Path
Word aligner, 8B/10B decoder, byte
deserializer, and phase
compensation FIFO
Custom single- and
double-width modes
Phase compensation FIFO, byte
serializer, and 8B/10B encoder
0.61 to ~6.5536
The same as custom single- and
double-width modes, plus rate
match FIFO and PIPE 2.0 interface
to the core logic
The same as custom single- and
double-width modes, plus PIPE 2.0
interface to the core logic
PCIe Gen1: x1, x2, x4, x8
PCIe Gen2: x1, x2, x4
2.5 and 5.0
1.25
(2)
The same as custom single- and
double-width modes, plus rate
match FIFO
The same as custom single- and
double-width modes
GbE
Arria V Device Handbook
February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
