Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
I/O Pin Leakage Current
The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all
VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).
10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed
when the diode is on.
Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when
the ADC IP core is enabled or disabled. This is applicable to all Intel MAX 10 devices with ADC IP core, which are 10M04,
10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A.
Table 10.
I/O Pin Leakage Current for Intel MAX 10 Devices
Symbol
Parameter
Input pin leakage current
Tristated I/O pin leakage current
Condition
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
–10
–10
Max
10
Unit
µA
II
IOZ
10
µA
Table 11.
ADC_VREF Pin Leakage Current for Intel MAX 10 Devices
Symbol
Iadc_vref
Parameter
ADC_VREF pin leakage current
Condition
Min
—
Max
10
Unit
µA
Single supply mode
Dual supply mode
—
20
µA
Bus Hold Parameters
Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed.
Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.
Intel® MAX® 10 FPGA Device Datasheet
10
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