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ASM705CSAF 参数 Datasheet PDF下载

ASM705CSAF图片预览
型号: ASM705CSAF
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗UP监控电路 [Low Power uP Supervisor Circuits]
分类和应用: 电源电路电源管理电路光电二极管监控输入元件
文件页数/大小: 16 页 / 199 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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ASM705 / 706 / 707 / 708  
ASM813L  
February 2005  
rev 1.5  
Pin Description  
Pin Number  
ASM707/708  
ASM705/706  
ASM813L  
Name  
Function  
DIP/  
DIP/  
SO  
DIP/  
SO  
MicroSO  
SO  
MicroSO  
MicroSO  
Manual reset input. The active LOW input triggers a reset  
pulse. A 250 µA pull-up current allows the pin to be  
driven by TTL/CMOS logic or shorted to ground with a  
switch.  
1
3
1
3
1
3
MR  
VCC  
2
3
4
5
2
3
4
5
2
3
4
5
+5V power supply input.  
GND  
Ground reference for all signals.  
Power-fail input voltage monitor. With PFI less than  
1.25V, PFO goes LOW. Connect PFI to Ground or VCC  
4
5
6
7
4
5
6
7
4
5
6
7
PFI  
when not in use.  
Power-fail output. The output is active LOW and sinks  
current when PFI is less than 1.25V.  
PFO  
Watchdog input. WDI controls the internal watchdog  
timer. A HIGH or LOW signal for 1.6sec at WDI allows  
the internal timer to run-out, setting WDO LOW. The  
watchdog function is disabled by floating WDI or by con-  
necting WDI to a high impedance three-state buffer. The  
internal watchdog timer clears when: RESET is asserted;  
WDI is three-stated ; or WDI sees a rising or falling edge.  
6
8
-
-
6
8
WDI  
-
-
6
7
8
1
-
-
-
-
NC  
Not Connected  
Active LOW reset output. Pulses LOW for 200ms when  
triggered, and stays LOW whenever VCC is below the  
reset threshold. RESET remains LOW for 200ms after  
7
1
RESET  
V
CC rises above the reset threshold or MR goes from  
LOW to HIGH. A watchdog timeout will not trigger  
RESET unless WDO is connected to MR.  
Watchdog output. WDO goes LOW when the 1.6 second  
internal watchdog timer times-out and does not go HIGH  
until the watchdog is cleared. In addition, when VCC falls  
8
-
2
-
-
-
8
7
2
1
WDO  
below the reset threshold, WDO goes LOW. Unlike  
RESET, WDO does not have a minimum pulse width and  
as soon as VCC exceeds the reset threshold, WDO goes  
HIGH with no delay.  
Active HIGH reset output. The inverse of RESET. The  
ASM813L only has a RESET output.  
8
2
RESET  
3 of 16  
Low Power µP Supervisor Circuits  
Notice: The information in this document is subject to change without notice  
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