April 2004
AS7C3256A
®
3.3V 32K X 8 CMOS SRAM (Common I/O)
Features
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil SOJ
- 8 × 13.4 mm TSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Pin compatible with AS7C3256
• Industrial and commercial temperature options
• Organization: 32,768 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Very low power consumption: ACTIVE
- 180mW max @ 10 ns
• Very low power consumption: STANDBY
- 7.2 mW max CMOS I/O
• Easy memory expansion with CE and OE inputs
Logic block diagram
Pin arrangement
28-pin TSOP 1 (8×13.4 mm)
V
28-pin SOJ (300 mil)
CC
GND
Input buffer
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
V
CC
WE
A13
A8
A9
A11
OE
OE
A11
A9
1
A10
CE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A0
A1
A8
4
I/O7
I/O0
A13
WE
5
6
A2
A3
A4
A5
A6
A7
256 X 128 X 8
Array
V
7
CC
8
A14
A12
A7
AS7C3256A
9
A10
CE
10
11
12
13
14
9
(262,144)
A6
A5
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A4
A1
A2
I/O0
I/O1
I/O2
GND
A3
17
16
15
WE
OE
CE
Column decoder
Control
circuit
A
8
A
9
A A A A A
10 11 12 13 14
Selection guide
-10
10
5
-12
12
6
-15
-20
Unit
ns
Maximum address access time
Maximum output enable access time
Maximum operating current
15
7
20
8
ns
50
2
45
2
40
2
35
2
mA
mA
Maximum CMOS standby current
4/23/04; v.2.0
Alliance Semiconductor
P. 1 of 9
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