May 2002
AS7C1024A
AS7C31024A
®
5V/ 3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024A (5V version)
• Latest 6T 0.25u CMOS technology
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/ LVTTL-compatible, three-state I/ O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• AS7C31024A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words x 8 bits
• High speed
- 10/ 12/ 15/ 20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 853 mW (AS7C1024A) / max @ 10 ns
- 522 mW (AS7C31024A) / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
Logic block diagram
V
A15
CE2
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/ O0
I/ O1
I/ O2
GND
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CC
WE
A13
A8
A9
VCC
A11
9
OE
A10
GND
10
11
12
13
14
15
16
CE1
Input buffer
I/ O7
I/ O6
I/ O5
I/ O4
I/ O3
A0
A1
A2
I/ O7
I/ O0
512
Array
(1,048,576)
×256×8
A3
A4
A5
A6
A7
A8
32-pin (8 x 20mm) TSOP I
32-pin (8 x 13.4mm) sTSOP1
A11
A9
1
OE
A10
CE1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
2
3
A8
4
A13
WE
CE2
A15
I/ O7
I/ O6
I/ O5
I/ O4
I/ O3
GND
I/ O2
I/ O1
I/ O0
A0
5
6
7
WE
Column decoder
8
V
CC
Control
circuit
OE
9
NC
10
11
12
13
14
15
16
A16
CE1
CE2
A14
A12
A7
A6
A1
18
17
A5
A2
A4
A3
Selection guide
-12
12
6
-15
15
7
-20
20
8
Unit
ns
-10
Maximum address access time
10
5
Maximum output enable access time
ns
AS7C1024A
AS7C31024A
AS7C1024A
AS7C31024A
155
145
10
5
150
140
10
5
145
135
10
5
140
130
10
5
mA
mA
mA
mA
Maximum
operating current
Maximum CMOS
standby current
9/ 26/ 02; 0.9.9
Alliance Semiconductor
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