March 2004
AS7C1026B
®
5 V 64K X 16 CMOS SRAM
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Features
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS I/O
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
A4
A3
A2
A1
A0
Logic block diagram
A0
CE
A1
A2
A3
A4
A5
A6
A7
V
CC
I/O0
I/O1
I/O2
I/O3
64 K × 16
Array
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
V
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
I/O0–I/O7
I/O8–I/O15
I/O
buffer
Control circuit
Column decoder
WE
UB
OE
LB
CE
Selection guide
-10
-12
12
6
-15
-20
20
8
Unit
ns
Maximum address access time
10
5
15
7
Maximum output enable access time
Maximum operating current
ns
110
10
100
10
90
10
80
10
mA
mA
Maximum CMOS standby current
3/26/04, v 1.3
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
