AS7C1024
AC test conditions
– Output load: see Figure B,
Thevenin Equivalent:
except for t and t see Figure C.
CLZ
CHZ
168Ω
D
+1.728V
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 5 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
out
+5V
+5V
480Ω
480Ω
D
D
out
out
+3.0V
90%
10%
90%
10%
255Ω
30 pF*
GND
255Ω
5 pF*
GND
*including scope
and jig capacitance
GND
Figure B: Output load
Figure C: Output load for t
, t
Figure A: Input waveform
CLZ CHZ
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, C.
tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed but not tested.
WE is HIGH for read cycle.
CE1 and OE are LOW and CE2 is HIGH for read cycle.
Address valid prior to or coincident with CE transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be HIGH or CE2 LOW during address transitions.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
6
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
