AS7C1024B
®
Functional description
The AS7C1024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8
bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high
performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
static, then full standby power is reached (ISB1). For example, the AS7C1024B is guaranteed not to exceed 55 mW under nominal full standby
conditions.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is
written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/
O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active,
output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter
Symbol
Min
–0.50
–0.50
–
Max
Unit
V
Voltage on V relative to GND
V
V
+7.0
CC
t1
t2
D
Voltage on any pin relative to GND
Power dissipation
V
+0.50
V
CC
P
T
1.0
+150
+125
20
W
Storage temperature (plastic)
–65
–55
–
°C
°C
mA
stg
bias
Ambient temperature with V applied
T
CC
DC current into outputs (low)
I
OUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Truth table
CE1
CE2
X
WE
X
OE
X
Data
Mode
Standby (I , I
H
High Z
High Z
High Z
)
)
SB SB1
X
L
X
X
Standby (I , I
SB SB1
L
H
H
H
Output disable (I
)
CC
L
H
H
L
D
Read (I
)
CC
OUT
L
H
L
X
D
Write (
)
IN
ICC
Key: X = don’t care, L = low, H = high
3/26/04, v 1.2
Alliance Semiconductor
P. 2 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
