AS7C1024A
AS7C31024A
®
ꢀꢀꢂꢉꢀꢆ
Write cycle (over the operating range)
-10
-12
-15
-20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tWC
tCW1
tCW2
tAW
tAS
10
8
8
8
0
7
0
0
5
0
–
1
–
–
–
–
–
–
–
–
–
–
6
–
12
10
10
9
–
–
–
–
–
–
–
–
–
–
6
–
15
12
12
10
0
–
–
–
–
–
–
–
–
–
–
6
–
20
12
12
12
0
–
–
–
–
–
–
–
–
–
–
8
–
Chip enable (CE1) to write end
Chip enable (CE2) to write end
Address setup to write end
Address setup time
12
12
0
12
Write pulse width
tWP
tWR
tAH
8
9
12
0
Write recovery time
0
0
Address hold from end of write
Data valid to write end
0
0
0
tDW
tDH
tWZ
tOW
6
8
10
0
Data hold time
0
0
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
–
–
–
1
1
2
ꢀꢈꢂꢀꢀꢂꢀꢆ
Write waveform 1 (WE controlled)
t
WC
t
WR
AH
t
t
AW
Address
WE
t
WP
t
AS
t
t
DW
DH
D
Data valid
IN
t
t
WZ
OW
D
OUT
ꢀꢈꢂꢀꢀꢂꢀꢆ
Write waveform 2 (CE1 and CE2 controlled)
t
WC
t
t
AH
WR
AW
t
Address
t
t
, t
AS
CW1 CW2
CE1
CE2
t
WP
WE
t
t
t
DH
WZ
DW
D
Data valid
IN
D
OUT
9/ 26/ 02; 0.9.9
Alliance Semiconductor
P. 5 of 9