AS7C1024A
AS7C31024A
®
AC test conditions
–
–
–
–
Output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168Ω
D
OUT
+1.728V (5V and 3.3V)
+5V
480Ω
+3.0V
GND
90%
10%
2 ns
90%
10%
D
OUT
255Ω
C(14)
D
OUT
255Ω
+3.3V
320Ω
C(14)
Figure A: Input pulse
GND
Figure B: 5V Output load
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
This parameter is sampled and not 100% tested.
For test conditions, see
AC Test Conditions,
Figures A, B, and C.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
CE1 and CE2 have identical timing.
C=30pF, except all high Z and low Z parameters, C=5pF.
2V data retention applies to commercial temperature operating range only.
9/26/02; 0.9.9
Alliance Semiconductor
P. 6 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
