AS6VB51216
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Functional description
The AS6VB51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288
words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/70/85 ns are ideal for low-power applications. Active high and low
chip enables (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems.
When CS1 is high or CS2 is low, or UB and LB are high, the device enters standby mode: the AS6VB51216 is guaranteed not to
exceed 66 µW power consumption at 3.3V. The device also retains data when VCC is reduced to 1.5V for even lower power
consumption.
The device can also be put into standby mode when deselected (CS1 is high or CS2 is low, or UB and LB are high). The input/
output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CS1 is high or CS2 is low, or UB and
LB are high), outputs are disabled (OE High), UB and LB are disabled (UB, LB High), or during a write operation ( CS1 is low or
CS2 is high and WE Low).
Writing to the device is accomplished by taking Chip Enables CS1 Low, CS2 High and Write Enable (WE) input Low. If Byte Low
Enable (LB) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0
through A18). If Byte High Enable (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location spec-
ified on the address pins (A0 through A18). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
Reading from the device is accomplished by taking Chip Enable CS1 Low, CS2 High and Output Enable (OE) Low while forcing
the Write Enable (WE) High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (UB) is Low, then data from memory will appear on I/O8 to I/O15.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the
JEDEC 48-ball FBGA package.
ꢌꢍꢎꢆꢂꢊꢄꢁꢈꢏꢐꢑꢅꢏꢊꢏꢈꢒꢐꢄꢅꢇꢉꢎ
Parameter
Voltage on VCC relative to VSS
Voltage on any I/O pin relative to GND
Power dissipation
Symbol
VtIN
Min
–0.5
–0.5
–
Max
VCC + 0.5
VCC + 0.5
1.0
Unit
V
VtI/O
PD
V
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
–65
–55
–
+150
°C
°C
mA
Tbias
IOUT
+125
20
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
1/21/02; V.0.9.6
Alliance Semiconductor
P. 2 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
