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AS6UA51216-70BC 参数 Datasheet PDF下载

AS6UA51216-70BC图片预览
型号: AS6UA51216-70BC
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, FBGA-48]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 9 页 / 205 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
 浏览型号AS6UA51216-70BC的Datasheet PDF文件第1页浏览型号AS6UA51216-70BC的Datasheet PDF文件第2页浏览型号AS6UA51216-70BC的Datasheet PDF文件第3页浏览型号AS6UA51216-70BC的Datasheet PDF文件第5页浏览型号AS6UA51216-70BC的Datasheet PDF文件第6页浏览型号AS6UA51216-70BC的Datasheet PDF文件第7页浏览型号AS6UA51216-70BC的Datasheet PDF文件第8页浏览型号AS6UA51216-70BC的Datasheet PDF文件第9页  
AS6UA51216  
Read cycle (over the operating range)  
–55  
–70  
–100  
Parameter  
Read cycle time  
Symbol  
tRC  
Min  
55  
Max  
Min  
70  
Max  
Min  
100  
Max  
Unit  
ns  
Notes  
Address access time  
tAA  
55  
55  
70  
70  
100  
100  
ns  
3
3
Chip enable (CS) access time  
tACS  
ns  
Output enable (OE) access  
time  
tOE  
tOH  
25  
35  
50  
ns  
ns  
Output hold from address  
change  
10  
10  
15  
5
CS  
o output in low Z  
tCLZ  
tCHZ  
tOLZ  
tBA  
10  
0
20  
10  
0
20  
10  
0
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4, 5  
4, 5  
4, 5  
CS high to output in high Z  
OE low to output in low Z  
UB/ LB access time  
5
5
5
55  
70  
100  
UB/ LB low to low Z  
UB/ LB high to high Z  
OE high to output in high Z  
Power up time  
tBLZ  
tBHZ  
tOHZ  
tPU  
10  
0
10  
0
10  
0
4, 5  
4, 5  
4, 5  
4, 5  
4, 5  
20  
20  
20  
20  
20  
20  
0
0
0
0
0
0
Power down time  
tPD  
55  
70  
100  
Shaded areas indicate preliminary information.  
Key to switching waveforms  
Rising input  
Falling input  
Undefined/ dont care  
Read waveform 1 (address controlled)  
t
RC  
Address  
t
AA  
t
t
OH  
OH  
D
Previous data valid  
Data valid  
OUT  
Read waveform 2 (CS, OE, UB, LB controlled)  
t
RC  
Address  
t
AA  
OE  
CS  
t
OE  
t
t
OH  
OLZ  
t
OHZ  
BHZ  
t
ACS  
t
t
HZ  
LZ  
LB, UB  
t
t
BA  
t
BLZ  
D
Data valid  
OUT  
4
ALLIANCE SEMICONDUCTOR  
6/ 27/ 00