AS6UA51216
Functional description
The AS6UA51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t , t , t ) of 55/ 70/ 100 ns are ideal for low-power applications. Active high and low chip enables
AA RC WC
(CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72 µW power
consumption at 3.6V and 55ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device also returns data when V is reduced
CC
to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/ or LB low. Data on the input pins I/ O1–
O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/ O
pins only after outputs have been disabled with output enable ( OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip
drives I/ O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/ O1–I/ O8, and UB controls the higher bits, I/ O9–I/ O16.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC
standard 400-mL, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.5
–0.5
–
Max
Unit
V
Voltage on VCC relative to V
V
VCC + 0.5
SS
tIN
Voltage on any I/ O pin relative to GND
Power dissipation
V
V
tI/ O
PD
1.0
+150
+125
20
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
Tbias
IOUT
–65
–55
–
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Supply
CS
H
L
WE
X
OE
X
LB
X
H
X
L
UB
X
H
X
H
L
Current I/ O1–I/ O8 I/ O9–I/ O16
Mode
ISB
High Z
High Z
Standby (ISB)
X
X
L
H
H
ICC
High Z
DOUT
High Z
High Z
DOUT
Output disable (ICC)
L
L
H
L
L
H
L
ICC
High Z
DOUT
Read (ICC)
Write (ICC)
L
DOUT
L
H
L
D
High Z
IN
X
H
L
ICC
High Z
D
IN
L
D
D
IN
IN
Key: X = Don’t care, L = Low, H = High.
2
ALLIANCE SEMICONDUCTOR
6/ 27/ 00
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
