AS6UA25617
Data retention characteristics (over the operating range)
Parameter
VCC for data retention
Data retention current
Sym
Test conditions
Min
1.2V
–
Max
3.6
2
Unit
V
VDR
VCC = 1.2V
CS1 ≥ VCC – 0.1V or
UB = LB > VCC – 0.1V
ICCDR
mA
ns
Chip deselect to data retention time tCDR
0
–
V
≥ VCC – 0.1V or
IN
Operation recovery time
tR
V
≤ 0.1V
tRC
–
ns
IN
Data retention waveform
Data retention mode
1.2V
V
V
V
CC
V
≥
CC
CC
DR
t
t
R
CDR
V
DR
V
V
IH
IH
CS1
CS2
V
V
IH
IH
V
DR
t
t
R
CDR
AC test loads and waveforms
R1
Thevenin equivalent:
R1
V
R
CC
V
TH
CC
V
OUTPUT
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
V
Typ
R2
CC
R2
90%
10%
90%
10%
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
< 5 ns
(c)
GND
(a)
(b)
Parameters
3.0V
1105
1550
645
2.5V
2.0V
15294
11300
6500
Unit
R1
R2
RTH
16670
15380
8000
Ohms
Ohms
Ohms
Volts
V
1.75V
1.2V
0.85V
TH
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS1 is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t are specified with C = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WEis HIGH for read cycle.
CS1 and OE are LOW and CS2 is HIGH for read cycle.
Address valid prior to or coincident with CS1 transition LOW and CS2 HIGH.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS1 or WE must be HIGH or CS2 LOW during address transitions. Either CS1 or WE asserting HIGH terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at HIGH Z and LOW Z parameters, where C = 5pF.
6
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
