May 2001
®
AS6UA25616
2.3V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable
‘Features
•
•
•
•
•
•
•
AS6UA25616
Intelliwatt™ active power circuitry
Industrial and commercial temperature ranges available
Organization: 262,144 words x 16 bits
2.7V to 3.6V at 55 ns
2.3V to 2.7V at 70 ns
Low power consumption: ACTIVE
- 114 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
• Low power consumption: STANDBY
- 72 µW max at 3.6V
- 41
µ
W max at 2.7V
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP 2
• ESD protection
≥
2000 volts
• Latch-up current
≥
200 mA
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
Row Decoder
V
CC
256K × 16
Array
(4,194,304)
V
SS
Pin arrangement (top view)
44-pin 400-mil TSOP 2
44
A4
1
A5
A6
43
A3
2
A7
42
A2
3
OE
41
A1
4
A0
5
40
UB
CS
6
39
LB
I/O16
7
38
I/O1
I/O15
8
37
I/O2
I/O14
I/O3
9
36
I/O13
I/O4
10
35
V
CC
V
SS
11
34
V
SS
V
CC
12
33
13
32
I/O5
I/O12
14
31
I/O6
I/O11
15
30
I/O7
I/O10
16
29
I/O8
I/O9
17
28
WE
NC
18
27
A8
A17
19
26
A9
A16
20
25
A10
A15
24
A11
A14
21
23
A12
A13
22
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
UB
OE
LB
CS
48-CSP Ball-Grid-Array Package
A
B
C
D
E
F
G
H
1
LB
I/O9
I/O10
V
SS
V
CC
I/O15
I/O16
NC
2
3
OE
A0
UB
A3
I/O11 A5
I/O12 A17
I/O13 NC
I/O14 A14
NC
A12
A8
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
I/O2
I/O4
I/O5
I/O6
WE
A11
6
NC
I/O1
I/O3
V
CC
V
SS
I/O7
I/O8
NC
Selection guide
V
CC
Range
Product
AS6UA25616
AS6UA25616
5/25/01; v.1.2
Power Dissipation
Max
(V)
3.6
2.7
Speed
(ns)
55
70
Operating (I
CC
)
Max (mA)
2
1
Standby (I
SB1
)
Max (
µ
A)
20
15
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
Min
(V)
2.7
2.3
Typ
2
(V)
3.0
2.5
Alliance Semiconductor
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
