JNaOnVuEaMryB2E0R027007
AS6C8016
512K X 8 BIT LOW POWER CMOS SRAM
512K X 16 BIT SUPER LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
tOH
Dout
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
LB#,UB#
tBA
OE#
tOE
tOH
tOLZ
tBLZ
tCLZ
tOHZ
tBHZ
tCHZ
High-Z
Dout
High-Z
Data Valid
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 5 of 12
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
