February 2007
®
AS6C6264
8K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
PARAMETER
Supply Voltage
V
CC
2.7
*1
Input High Voltage
V
IH
0.7*Vcc
*2
Input Low Voltage
V
IL
- 0.5
V
CC
≧
V
IN
≧
V
SS
Input Leakage Current
I
LI
-1
Output Leakage
V
CC
≧
V
OUT
≧
V
SS,
I
LO
-1
Current
Output Disabled
Output High Voltage
V
OH
I
OH
= -1mA
2.4
Output Low Voltage
V
OL
I
OL
= 2mA
-
Cycle time = Min.
CE# = V
IL
and CE2 = V
IH
, - 55
I
CC
-
I
I/O
= 0mA
Average Operating
Cycle time = 1µs
Power supply Current
CE#
≦
0.2V and CE2
≧
V
CC
-0.2V,
I
CC1
-
I
I/O
= 0mA
other pins at 0.2V or V
CC
-0.2V
-C
CE#
≧
V
CC
-0.2V
Standby Power
I
SB1
Supply Current
or CE2
≦
0.2V
-I
-
Notes: C = Commercial Temperature I = Industrial temperature
.0V for pul e width le than 10ns
s
ss
.
1. V (max) = V + 3
IH
CC
2. V (min) = V - 3.0V for pulse idth less than
w
10ns.
IL
SS
3. Over/ ndershoot specificationsare charact rized, not 10% tes
U
e
0
ted.
4. 10 A for special reque
st
µ
5. Typical valuesare included for
reference on a are not
ly nd
guaranteed or tested.
Typical valued are measuredt a
CC
= V (TYP.) and T
A
= 25ºC
V
CC
TYP.
3.0
-
-
-
-
3.0
-
15
*5
MAX.
5.5
V
CC
+0.3
0.6
1
1
-
0.4
45
UNIT
V
V
V
µA
µA
V
V
mA
3
1
1
10
50
*4
80
*4
mA
µA
µA
CAPACITANCE
(T
A
= 25
℃
, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note :These parameters areguaranteed by devic characterization, but notroduction tested.
e
p
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 50pF + 1TTL, I
OH
/I
OL
= -1mA/2mA
02/Feb/07, v1.0
Alliance Memory Inc
Page 3 of 12
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
