JFaEnBuRaUrAyR2Y0027009
AS6C1616
512K X 8 BI T LOW POWER CMOS SRAM
1024K X 16 BIT LOW POWER CMOS SRAM
WRITE CYCLE 3
(LB#,UB# Controlled)
(1,2,5,6)
tWC
Address
CE#
tAW
tWR
tAS
tCW
CE2
tBW
LB#,UB#
tWP
WE#
Dout
tWHZ
High-Z
(4)
tDW
tDH
Din
Data Valid
Notes :
1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain
in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
FEBRUARY/2009, V 1.a
Alliance Memory Inc.
Page 7 of 11
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
