February 2007
®
AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
Data Retention Current
SYMBOL
V
DR
I
DR
TEST CONDITION
CE#
≧
V
CC
- 0.2V
or CE2
≦
0.2V
C**
I**
0
t
RC
*
MIN.
1.5
-
TYP.
-
0.5
0
-
-
MAX.
5.5
1
3
-
-
UNIT
V
µ
µA
ns
ns
V
CC
= 1.5V
CE#
≧
V
CC
- 0.2V
or CE2
≦
0.2V
See Data Retention
Chip Disable to Data
t
CDR
Waveforms (below)
Retention Time
Recovery Time
t
R
t
RC
*
= Read Cycle Time
C=Commercial temp/I = Industrial temp**
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE#
controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE#
V
IH
CE#
≧
Vcc-0.2V
Vcc(min.)
t
R
V
IH
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE2
CE2
≦
0.2V
V
IL
V
IL
Vcc(min.)
t
R
02/February/07, v 1.0
Alliance Memory Inc.
Page 7 of 14
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
