AS4LC2M8S1
AS4LC1M16S1
®
Operating modes
Command
CKEn-1 CKEn
CS
L
RAS
L
CAS
L
WE DQM A11
A10 A9–A0 Note
Mode register set
H
H
H
X
H
L
L
X
X
X
X
X
X
Op code
1,2
3
Auto refresh
L
L
L
H
H
H
X
X
X
X
X
Entry
Exit
L
L
L
3
Self
refresh
L
H
X
H
X
3
L
H
X
X
H
L
3
Bank activate
H
H
L
H
H
V*
V
row address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
column
address
Read
L
H
L
H
X
column
address
Write
H
H
H
X
X
X
L
L
L
H
H
L
L
L
L
L
X
X
X
V
H
4,5
6
Burst stop
Precharge
H
H
X
Selected bank
Both banks
V
X
L
X
H
H
L
X
V
X
X
H
X
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
X
X
X
X
X
X
V
X
X
Entry
Exit
H
L
L
H
L
Clock suspend or
active power down
X
X
H
L
Entry
H
Precharge power
down mode
X
H
L
Exit
L
H
X
X
DQM
H
H
X
H
L
X
X
X
7
No operation command
X
* V = Valid.
1
OP= operation code.
A0~A11 see page 5.
2
3
MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS.
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after both banks are precharged.
4
5
A11: bank select address. If low during read, write, row active and precharge, bank A is selected.
If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge.
A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t from the end of the burst.
RP
6
7
Burst stop command valid at every burst length except full-page burst.
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
5/21/01; v.1.1
Alliance Semiconductor
P. 4 of 29
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
