AS4LC256K16EO
®
Notes
1
2
3
I
I
, I , I , and I
depend on cycle rate.
CC6
CC1 CC3 CC4
and I
depend on output loading. Specified values are obtained with the output open.
CC4
CC1
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume t = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, V (min) ≥ GND and V (max)
T
IL
IH
≤ V
.
CC
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
I
H
I
L
I
H
I
L
Operation within the t
specified t
(max) limit insures that t
(max) limit, then access time is controlled exclusively by t
(max) can be met. t
(max) is specified as a reference point only. If t
(max) is specified as a reference point only. If t
is greater than the
is greater than the
RCD
RAC
RCD
.
RCD
RCD
CAC
7
Operation within the t
(max) limit insures that t
(max) can be met. t
RAC RAD
RAD
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
11
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
OFF
t
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ t
AWD WS
WCS WCH RWD CWD
(min) and t ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
≥ t
WH
WH
RWD
(min), tCWD ≥ t
(min) and tAWD ≥ t (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.
RWD
CWD
AWD
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t or t or t
.
CAP
CAA
CAC
14
t
ASC ≥ t to achieve t (min) and t
(max) values.
CAP
CP
PC
15 These parameters are sampled and not 100% tested.
Key to switching waveform
Undefined/don’t care
Rising input
Falling input
Read cycle waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tASC
tRCS
tCAH
tCRP
tCAS
UCAS
,
tAR
LCAS
tRAD
tRAL
tASR
tRAH
Row Address
Address
Col Address
tRRH
tRCH
WE
OE
tROH
tOEZ
tRAC
tAA
tOFF
tOEA
tCAC
tCLZ
Data Out
I/O
4/11/01; V.1.1
Alliance Semiconductor
P. 8 of 25
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
