AS4LC4M4F1
®
Notes
1
2
3
I
CC1
, I
CC3
, I
CC4
, and I
CC6
are dependent on frequency.
I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the output open.
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
AC Characteristics assume t
T
= 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V
IL
(min)
≥
GND and V
IH
(max)
≤
V
CC
.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and V
IL
.
Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference point only. If t
RCD
is greater than the
specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as a reference point only. If t
RAD
is greater than the
specified t
RAD
(max) limit, then access time is controlled exclusively by t
AA
.
Assumes three state test load (5 pF and a 380
Ω
Thevenin equivalent).
Either t
RCH
or t
RRH
must be satisfied for a read cycle.
t
OFF
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
OFF
is referenced from
rising edge of RAS or CAS, whichever occurs last.
t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If t
WS
≥
t
WS
(min) and t
WH
≥
t
WH
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min) and t
AWD
≥
t
AWD
(min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
Access time is determined by the longest of t
CAA
or t
CAC
or t
CPA
t
ASC
≥
t
CP
to achieve t
PC
(min) and t
CPA
(max) values.
These parameters are sampled and not 100% tested.
4
5
6
7
8
9
10
11
12
13
14
15
AC test conditions
- Access times are measured with output reference levels of
V
OH
= 2.4V and V
OL
= 0.4V,
V
IH
= 2.0V and V
IL
= 0.8V
- Input rise and fall times: 2 ns
+3.3V
R1 = 828
Ω
D
out
50 pF*
R2 = 295
Ω
GND
Figure A: Equivalent output load
(AS4LC4M4F1)
*including scope
and jig capacitance
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
5/16/01; v.1.0 Restored
Alliance Semiconductor
P. 7 of 14
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
