AS4LC2M8S1
AS4LC1M16S1
®
Operating modes
Command
Mode register set
Auto refresh
Entry
Self
refresh
Bank activate
Read
Write
Burst stop
Precharge
Selected bank
Both banks
Entry
Exit
Entry
Precharge power
down mode
Exit
DQM
No operation command
* V = Valid.
CKEn-1 CKEn
H
H
H
L
H
H
H
H
H
H
L
H
L
H
H
X
H
L
H
X
X
X
X
X
L
H
L
H
X
X
CS
L
L
L
L
H
L
L
L
L
L
H
L
X
H
L
H
L
X
H
L
RAS
L
L
L
H
X
L
H
H
H
L
X
V
X
X
H
X
H
X
X
H
CAS
L
L
L
H
X
H
L
L
H
H
X
V
X
X
H
X
H
X
X
H
WE
L
H
H
H
X
H
H
L
L
L
X
V
X
X
H
X
H
X
X
H
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
A11
A10
Op code
X
X
X
X
A9–A0
Note
1,2
3
3
3
3
4
4,5
4
4,5
6
Exit
V
*
V
V
row address
L
H
L
H
X
L
H
X
column
address
column
address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
V
X
X
Clock suspend or
active power down
X
X
X
X
X
7
1
2
3
4
5
6
7
OP= operation code.
A0~A11 see page 5.
MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS.
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after both banks are precharged.
A11: bank select address. If low during read, write, row active and precharge, bank A is selected.
If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge.
A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t
RP
from the end of the burst.
Burst stop command valid at every burst length except full-page burst.
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
5/21/01; v.1.1
Alliance Semiconductor
P. 4 of 29
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
