AS4LC4M16S0
AS4LC16M4S0
®
Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access
Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks,
respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the
rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a
new column address.
The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving
operations. This provides a significant advantage over asynchronous EDO and fast page mode devices.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length
and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency
improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of
applications.
DRAM commands and functions are decoded from control inputs. Basic commands are as follows:
• Deactivate all banks
• Select row; activate bank
• CBR refresh
• Mode register set
• Deactivate bank
• Deselect; power down
• Select column; write
• Select column; read
• Auto precharge with read/ write • Self-refresh
The 64 Mb DRAM devices are available in 400-mil plastic TSOP II packages and have 54 pins in each configuration. Both
devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise
and EMI. Inputs and outputs are LVTTL-compatible.
Logic block diagram
CLK
Clock generator
CKE
BA0, BA1
Bank select
A[11:0]
Row
address
buffer
†
Bank A 1M×16
(4096×256×16)
†
Bank B 1M×16
(4096×256×16)
Mode register
Bank C† 1M×16
(4096×256×16)
Refresh
counter
Bank D† 1M×16
(4096×256×16)
Sense amplifier
CS
‡
Column decoder and
latch circuit
DQM
Column
address
buffer
RAS
CAS
Data control circuit
DQ
Burst
counter
WE
†
‡
For AS4LC8M8S0, Banks A-D will read 8M×8 (4096×512×8).
For AS4LC4M16S0, DQM will be UDQM and LDQM.
2
ALLIANCE SEMICONDUCTOR
7/ 5/ 00
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
