®
AS4LC8M8S0
AS4LC4M16S0
I
DD
specifications and conditions
(0° C
≤
T
A
≤
70° C, V
DD
, V
DDQ
= +3.3V ± 0.3V)
Max
Parameter
Operating current: active mode; burst = 2; READ or WRITE;
t
RC
= t
RC
(min); CAS latency = 3
Standby current: power-down mode; all banks idle;
CKE = low
Standby current: active mode; CKE = high; CS# = high; all
banks active after t
RCD
met; no accesses in progress
Operating current: burst mode; continuous burst; READ or
WRITE; all banks active; CAS latency = 3
Auto refresh current: CKE = high;
CS# = high
Self-refresh current: CKE
≤
0.2V
t
RFC
= t
RFC
(min);
CL = 3
t
RFC
= 15.625ms;
CL = 3
Symbol
I
DD1
I
DD2
I
DD3
I
DD4
I
DD5
I
DD6
I
DD7
–75
115
2
45
140
210
50
1
–8
95
2
35
130
210
50
1
–10F/10
95
2
35
120
190
40
1
Units
mA
mA
mA
mA
mA
mA
mA
Notes
4, 5
4,5
4, 5
4,5
4, 5
4,5
4,5
Notes
1 I
DD
specifications are tested after proper initialization of the device.
2 I
DD
is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open.
3 I
DD
tests have V
IL
= 0V and V
IH
= 3V.
4 I
DD
current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time.
5 Address transitions average one transition every two clock cycles.
7/5/00
ALLIANCE SEMICONDUCTOR
7
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
