AS4LC2M8S1
AS4LC1M16S1
–7
–8
–10
CAS
Sym
Parameter
latency Min
Max
–
Min
2
Max
–
Min
2
Max
–
Unit
tCK
Notes
5
Load mode register to
active/ refresh command
tMRD
2
3
2
1
2
2
2
–
–
–
2.5
2.5
2.5
–
–
–
3
3
3
–
–
–
ns
ns
ns
6
6
6
Output data hold time @
30 pF
tOH
CKE to CLOCK enable or
power-down exit mode
tPED
1
–
1
–
1
–
tCK
Active to precharge
command
tRAS
42 120,000
48
120,000
50
120,000 ns
tRC Active command period
tRCAR Auto refresh period
70
70
–
–
80
80
–
–
80
80
–
–
ns
ns
8
8
Active to read or write
delay
tRCD
20
–
–
24
–
–
30
–
–
ns
Refresh period—2048
rows
tREF
64
64
64
ms
3
2
1
3
2
1
–
–
–
3
2
1
–
–
–
3
2
1
–
–
–
tCK
tCK
tCK
9
9
9
Data-out high Z from
tROH precharge/ burst stop
command
Precharge command
period
tRP
21
14
–
–
24
16
–
–
30
20
–
–
ns
ns
8
Active Bank A to Active
tRRD
Bank B command
tT Transition time
0.3
2
1.0
–
0.3
2
1.0
–
0.3
2
1.0
–
ns
tWR WRITE recovery time
tCK
Exit SELF REFRESH to
tXSR
70
–
80
–
80
–
ns
20
ACTIVE command
Notes
1
2
3
4
5
6
7
8
I
is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
DD
Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid V or V levels.
IH IL
Address transitions average one transition every two-clock period.
The I current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-l atency is reduced.
DD
= 7 ns for –7, 8 ns for –8, and 10 ns for –10.
t
CK
If clock t > 1 ns, (t – 0.5)ns should be added to the parameter.
r
r/ 2
If clock (t and t ) > 1 ns, [(t + t )/ 2 – 1] ns should be added to the parameter.
r
f
r
f
V
overshoot: V
= V
+ 2V for a pulse width ≤ 3 ns, and the pulse width cannot be greater than one third of the cycle rate. V undershoot:
IH
IH(max)
DDQ
IL
V
= –2V for a pulse width ≤ 3 ns and the pulse width cannot be greater than one third of the cycle rate.
IL(min)
Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter.
9
10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including t
used to reduce the data rate.
and PRECHARGE commands). CKE may be
WR
11 Timing actually specified t plus t ; clock(s) specified as a reference only at minimum cycle rate.
WR RP
12 Timing actually specified by t
.
WR
13
t
defines the time at which the output achieves the open circuit condition; it is not a reference to V or V . The last valid data element will meet t
OH OL OH
HZ
before going to HIGH-Z.
14 CLK must be toggled a minimum of two times during this period.
15 Enables on-chip refresh and address counters.
16 All voltages referenced to V .
SS
17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0 ° C ≤ T ≤ 70° C) is
A
endured.
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
