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• Organization:
1,048,576 words × 8 bits × 2 banks (2M×8)
524,288 words × 16 bits × 2 banks (1M×16)
• All signals referenced to positive edge of clock
• Dual internal banks controlled by A11 (bank select)
• High speed
- 125/100/83 MHz
- 6/7/8.5 ns clock access time
• Low power consumption
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
•
•
•
•
•
•
Automatic and direct precharge
Burst read, single write
Can assert random column address in every cycle
LVTTL compatible I/O
3.3V power supply
JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP II (2M×8)
- 400 mil, 50-pin TSOP II (1M×16)
Read/write data masking
Programmable burst length (1/2/4/8/full page)
Programmable burst sequence (sequential/interleaved)
Programmable CAS latency (1/2/3)
•
•
•
•
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TSOP II
V
CC
DQ0
V
SSQ
DQ1
V
CCQ
DQ2
V
SSQ
DQ3
V
CCQ
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ7
V
SSQ
DQ6
V
CCQ
DQ5
V
SSQ
DQ4
V
CCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
CCQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
CCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
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TSOP II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
CCQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
CCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
Pin(s)
DQM (2M×8)
UDQM/LDQM (1M×16)
A0 to A10
A11
DQ0 to DQ7 (2M×8)
DQ0 to DQ15 (1M×16)
RAS
CAS
WE
CS
V
CC
, V
CCQ
V
SS
, V
SSQ
CLK
CKE
Description
Output disable/write mask
Address inputs
Bank select
Input/output
Row address strobe
Column address strobe
Write enable
Chip select
Power (3.3V ± 0.3V)
Ground
Clock input
Clock enable
'5$0
'5$0
'5$0
'5$0
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Symbol
Bus frequency (CL = 3)
Maximum clock access time (CL = 3)
Minimum input setup time
Minimum input hold time
Row cycle time (CL=3, BL=1)
Maximum operating current
Maximum CMOS standby current, self refresh
f
max
t
AC
t
S
t
H
t
RC
I
CC1
I
CC6
AS4LC2M8S0-8
125
6
2
1.0
72
100
1
AS4LC2M8S0-10
100
7
2
1.0
80
80
1
AS4LC2M8S0-12
83.3
8.5
3.0
1.0
90
75
1
Unit
MHz
ns
ns
ns
ns
mA
mA
AS4LC1M16S0
A
S4LC2M8S0
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Copyright ©1998 Alliance Semiconductor. All rights reserved.
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
