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Command
Pin settings
Description
The Bank Precharge command precharges the bank specified by A11. The
precharged bank is switched from active to idle state and is ready to be activated
again. Assert the precharge command after tRAS(min) of the bank activate
command in the specified bank. The precharge operation requires a time of
tRP(min) to complete.
CS = A10 = RAS = WE =
low; CAS = high; A11 =
bank select; A0~A9 = don’t
care
Bank
precharge
CS = RAS = WE = low; CAS
Precharge all = A10 = high; A11 = bank
select; A0~A9 = don’t care
The Precharge All command precharges both banks simultaneously. Both banks
are switched to the idle state on precharge completion.
CS = CAS = WE (write) =
low; RAS = WE (read) =
A10 = high; A11 = bank
During auto precharge, the SDRAM adjusts internal timing to satisfy tRAS(min)
and tRP for the programmed CAS latency and burst length. Couple the auto
precharge with a burst read/ write operation by asserting A10 to a high state at
the same time the burst read/ write commands are issued. At auto precharge
completion, the specified bank is switched from active to idle state. Note that no
new commands can be issued until the specified bank achieves the idle state
Auto
select; A0~A9 = column
precharge
address; (A9 = don’t care
for 2M×8; A8,A9 = don’t
care for 1M×16)
When CKE is low, the internal clock is frozen or suspended from the next clock
cycle and the state of the output and burst address are frozen. If both banks are
idle and CKE goes low,the SDRAM enters power down mode at the next clock
cycle. When in power down mode, no input commands are acknowledged as
long as CKE remains low. To exit power down mode, raise CKE high before the
rising edge of CLK.
Clock
suspend/
CKE = low
power down
mode entry
Clock
Resume internal clock operation by asserting CKE high before the rising edge of
CLK. Subsequent commands can be issued one clock cycle after the end of the
Exit command.
suspend/
CKE = high
power down
mode exit
SDRAM storage cells must be refreshed every 64ms to maintain data integrity.
Use the Auto Refresh command to accomplish the refreshing of all rows in both
banks of the SDRAM. The row address is provided by an internal counter which
CS = RAS = CAS = low; WE increments automatically. Auto refresh can only be asserted when both banks are
Auto refresh = CKE = high; A0~A11 = idle and the device is not in the power down mode. The time required to
don’t care
complete the auto refresh operation is tRC(min). Use NOPs in the interim until
the auto refresh operation is complete. This is the most common refresh mode.
It is typically performed once every 15.6us or in a burst of 4096 auto refresh
cycles every 64ms. Both banks will be in the idle state after this operation.
Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh
address and timing are provided internally. Self refresh entry is allowed only
when both banks are idle. The internal clock and all input buffers with the
exception of CKE are disabled in this mode. Exit self refresh by restarting the
external clock and then asserting CKE high. NOP’s must follow for a time of
CS = RAS = CAS = CKE =
low; WE = high; A0~A11
= don’t care
Self refresh
t
RC(min) for the SDRAM to reach the idle state where normal operation is
allowed. If burst auto refresh is used in normal operation, burst 4096 auto
refresh cycles immediately after exiting self refresh.
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ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
