AS4LC2M8S1
AS4LC1M16S1
Pin descriptions
Pin
Name
Description
CLK
System clock
All operations synchronized to rising edge of CLK.
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. If both banks
are idle and CKE goes low, the SDRAM will enter power down mode
from the next clock cycle. When in power down mode and CKE is
low, no input commands will be acknowledged. To exit power down
mode, raise CKE high before the rising edge of CLK.
CKE
Clock enable
Enables or disables device operation by masking or enabling all
inputs except CLK, CKE, UDQM/ LDQM (×16), DQM (×8).
CS
Chip select
Address
Row and column addresses are multiplexed. Row address: A0~A10.
Column address (2M × 8): A0~A8. Column address (1M × 16):
A0~A7.
A0~A10
Memory cell array is organized in 2 banks. A11 selects which internal
bank will be active. A11 is latched during bank activate, read, write,
mode register set, and precharge operations. Asserting A11 low
selects Bank A; A11 high selects Bank B.
A11
Bank select
RAS
CAS
WE
Row address strobe
Column address strobe
Write enable
Command inputs.
RAS, CAS, and WE, along with CS, define the command being
entered.
Controls I/ O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
For ×16, LDQM controls the lower byte (DQ0 – 7) and UDQM
controls the upper byte (DQ8 – 15). UDQM and LDQM are
considered to be in the same state when referred to jointly as DQM.
×8: DQM
×16: UDQM, LDQM
Output disable/ write mask
DQ0~DQ15
Data input/ output
Data inputs/ outputs are multiplexed.
VCC/ V
Power supply/ ground
Power and ground for core logic and input buffers.
SS
V
CCQ/ V
Data output power/ ground Power and ground for data output buffers.
SSQ
7/ 5/ 00
ALLIANCE SEMICONDUCTOR
3
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
