AS4C4M4EOQ
AS4C4M4E1Q
®
Logic block diagram for 4K refresh
Data
I/O
buffers
VCC
Column decoder
Sense amp
GND
I/O0 to I/O3
RAS clock
generator
RAS
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
4,194,304 × 4
Array
CAS clock
generator
(16,777,216)
A9
A10
A11
WE clock
generator
WE
Logic block diagram for 2K refresh
Data
I/O
buffers
VCC
Column decoder
Sense amp
GND
I/O0 to I/O3
RAS clock
generator
RAS
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
4,194,304 × 4
Array
CAS clock
generator
(16,777,216)
A9
A10
Substrate bias
generator
WE clock
generator
WE
Recommended operating conditions
Parameter
Symbol
VCC
Min
Nominal
Max
5.5
Unit
V
4C4M4EOQ
AS4C4M4E1Q
4.5
0.0
2.4
5.0
0.0
–
Supply voltage
GND
VIH
0.0
V
4C4M4EOQ
AS4C4M4E1Q
VCC
V
Input voltage
VIL
TA
–0.5†
0
–
0.8
70
V
Ambient operating temperature
°C
†
V
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
IL
3/22/01; v.1.0
Alliance Semiconductor
P. 3 of 16
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
