AS4C8M16D1
Pin Descriptions
Table 1. Pin Details
Symbol
CK,
Type
Description
are driven by the system clock. All SDRAM input signals are
CK
Input
Differential Clock: CK,
CK
sampled on the positive edge of CK. Both CK and
and controls the output registers.
increment the internal burst counter
CK
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
low synchronously with clock, the internal clock is suspended from the next clock cycle
and the state of output and burst address is frozen as long as the CKE remains low. When
all banks are in the idle state, deactivating the clock controls the entry to the Power Down
and Self Refresh modes.
BA0, BA1
A0-A11
Input
Input
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A11 are sampled during the BankActivate command (row address
A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto
Precharge).
Input
Input
Chip Select:
enables (sampled LOW) and disables (sampled HIGH) the command
CS
CS
decoder. All commands are masked when
CS
bank selection on systems with multiple banks. It is considered part of the command code.
is sampled HIGH.
provides for external
CS
Row Address Strobe: The signal defines the operation commands in conjunction
RAS
RAS
with the
and
WE
signals and is latched at the positive edges of CK. When
CAS
RAS
is asserted "HIGH," either the BankActivate
CAS
and
are asserted "LOW" and
CS
command or the Precharge command is selected by the
signal. When the
is
WE
WE
asserted "HIGH," the BankActivate command is selected and the bank designated by BA
is turned on to the active state. When the is asserted "LOW," the Precharge
WE
command is selected and the bank designated by BA is switched to the idle state after the
precharge operation.
Input
Input
Column Address Strobe: The
signal defines the operation commands in
CAS
CAS
WE
conjunction with the
and
signals and is latched at the positive edges of CK.
is asserted "LOW," the column access is started by
RAS
WE
When
is held "HIGH" and
RAS
CS
asserting
"LOW." Then, the Read or Write command is selected by asserting
CAS
WE
"HIGH” or “LOW".
Write Enable: The
signal defines the operation commands in conjunction with the
WE
and
signals and is latched at the positive edges of CK. The
input is used
WE
RAS
CAS
to select the BankActivate or Precharge command and Read or Write command.
LDQS,
UDQS
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe
is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM.
LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
UDM
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15
Input /
Output
Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and
negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes.
VDD
VSS
Supply
Supply
Supply
Power Supply: +2.5V 5%
Ground
VDDQ
DQ Power: +2.5V 5%. Provide isolated power to DQs for improved noise immunity.
Alliance Memory Inc. Confidential
4
Rev. 1.1
Feb. /2009
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
