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CK,
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Input
'LIIHUHQWLDOꢀ &ORFNꢐ CK,
are driven by the system clock. All SDRAM input signals are
CK
CK
sampled on the positive edge of CK. Both CK and
and controls the output registers.
increment the internal burst counter
CK
CKE
Input
&ORFNꢀ (QDEOHꢐ CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
low synchronously with clock, the internal clock is suspended from the next clock cycle and
the state of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power Down and
Self Refresh modes.
BA0, BA1
A0-A11
Input
Input
Input
%DQNꢀ $FWLYDWHꢐ BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
$GGUHVVꢀ,QSXWVꢐꢀA0-A11 are sampled during the BankActivate command (row address A0-
A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge).
&KLSꢀ6HOHFWꢐ
enables (sampled LOW) and disables (sampled HIGH) the command
CS
CS
decoder. All commands are masked when
is sampled HIGH.
provides for external
CS
CS
bank selection on systems with multiple banks. It is considered part of the command code.
Input
5RZꢀ $GGUHVVꢀ 6WUREHꢐ The
signal defines the operation commands in conjunction
RAS
RAS
with the
and
signals and is latched at the positive edges of CK. When
and
WE
CAS
RAS
is asserted "HIGH," either the BankActivate command or
are asserted "LOW" and
CS
CAS
the Precharge command is selected by the
signal. When the
is asserted "HIGH,"
WE
WE
the BankActivate command is selected and the bank designated by BA is turned on to the
active state. When the is asserted "LOW," the Precharge command is selected and
WE
the bank designated by BA is switched to the idle state after the precharge operation.
Input
Input
&ROXPQꢀ$GGUHVVꢀ6WUREHꢐ The signal defines the operation commands in conjunction
CAS
CAS
signals and is latched at the positive edges of CK. When
with the
and
is
WE
is asserted "LOW," the column access is started by asserting
RAS
held "HIGH" and
RAS
CS
CAS
"LOW." Then, the Read or Write command is selected by asserting
"HIGHÓ or ÒLOW".
WE
:ULWHꢀ (QDEOHꢐꢀ The
signal defines the operation commands in conjunction with the
WE
WE
signals and is latched at the positive edges of CK. The
CAS
and
input is used
WE
RAS
to select the BankActivate or Precharge command and Read or Write command.
LDQS,
UDQS
Input /
Output
%LGLUHFWLRQDOꢀ'DWDꢀ6WUREHꢐꢀSpecifies timing for Input and Output data. Read Data Strobe is
edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS
is for DQ0~7, UDQS is for DQ8~15.
LDM,
UDM
Input
'DWDꢀ,QSXWꢀ0DVNꢐꢀ Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15
Input / 'DWDꢀ ,ꢏ2ꢐꢀ The DQ0-DQ15 input and output data are synchronized with positive and
Output negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes.
VDD
VSS
Supply
Supply *URXQGꢀ
Supply
Supply '4ꢀ*URXQGꢐꢀProvide isolated ground to DQs for improved noise immunity.ꢀ
Supply 5HIHUHQFHꢀ9ROWDJHꢀIRUꢀ,QSXWVꢐꢀ+0.5*VDDQ
1Rꢀ&RQQHFWꢐꢀNo internal connection, these pins suggest to be left unconnected.ꢀ
3RZHUꢀ6XSSO\ꢐꢀ+2.5V ± 0.2Vꢀ
VDDQ
VSSQ
VREF
NC
'4ꢀ3RZHUꢐꢀ+2.5V ± 0.2V. Provide isolated power to DQs for improved noise immunity.ꢀ
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ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
